Recent advances in integrated circuit fabrication technology have increasingly allowed more circuits to be manufactured in smaller areas. These technological advances have resulted in two trends in commercial integrated circuit data processors. First, data processors have combined central processing units (CPUs) with other computer system components such as memory and peripheral circuits on a single integrated circuit chip. For example, the data processor will typically incorporate some form of nonvolatile memory on-chip to store its operating program. Many forms of nonvolatile memory exist, such as read only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM or E.sup.2 PROM), flash EEPROM or E.sup.2 PROM, and the like. Besides reducing the cost of the data processor, on-chip nonvolatile memory may be accessed faster than comparable external memory.
The second trend involves the increasing sophistication of the CPU. Early data processors incorporated simple CPUs having single 8-bit data paths and simple instruction sets. More recently, data processors have been built using CPUs with 16- and 32-bit data paths with full Harvard bus architectures (separate instruction and data buses) and supporting reduced instruction set computer (RISC) programming.
However, the increasing integration of components and sophistication of CPUs have created new problems which demand new solutions. One of these problems relates to the fact that data processors frequently incorporate nonvolatile memory on-chip in order to store program instructions. During system development, it is helpful for the data processor to get the control program from external memory rather than nonvolatile memory. Thus, a useful feature is the ability to cause accesses to the on-chip nonvolatile memory to be routed off-chip. In this way, the program may be modified until it works correctly. Once the program is debugged, it may be loaded into the on-chip nonvolatile memory.
One example of a data processor with on-chip memory which allows accesses to on-chip memory to be selectively re-routed off-chip is the DSP56000 available from Motorola, Inc. The DSP56000 is has dual internal data buses each connecting to its own nonvolatile memory. A control register includes a control bit known as the development mode or "DE" bit which, when set, causes memory accesses to the internal nonvolatile memories to be re-routed to an external memory.
Another reason to route accesses off-chip relates to the fact that certain operating parameters are frequently stored in nonvolatile memory. For example, in the case of an automobile engine controller, these operating parameters might include spark and fuel timing profiles over different operating conditions such as temperature, engine speed (revolutions per minute or RPMs), engine load, atmospheric pressure, etc. During the lifetime of the automobile, it may be necessary to re-calibrate these operating parameters to reflect changes in the system. Thus, it would generally be desirable for an access by the CPU to an operating parameter stored in nonvolatile memory to be selectively routed off-chip. Then, the parameter value can be optimized and then re-stored in the on-chip nonvolatile memory.
However, storing parameters in the same nonvolatile memory as the program creates a problem when the parameters are re-calibrated. Off-chip accesses to the nonvolatile memory change the operation of the program itself because off-chip accesses take longer than accesses to the internal memory. If the system is re-calibrated while the program is running from off-chip memory, then the calibrated parameter values may not be optimal when the program is again run from internal memory. What is needed then is an integrated circuit data processor which allows the use of a single nonvolatile memory but which allows more exact calibration of parameters. The present invention provides such an integrated circuit data processor, and these and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.